Method of manufacture of a trench-gate semiconductor device

ABSTRACT

A method of making a trench MOSFET includes forming a layer of porous silicon ( 26 ) at the bottom of a trench and then oxidizing the layer of porous silicon ( 26 ) to form a plug ( 30 ) at the bottom of the trench. This forms a thick oxide plug at the bottom of the trench thereby reducing capacitance between gate and drain.

The invention relates to the method of manufacture of a semiconductordevice incorporating a trench, particularly a trench MOSFET (metal oxidesemiconductor field effect transistor).

An example of a prior art trench semiconductor structure is illustratedin FIG. 4. An n-type drain layer 4 is provided over an n+ substrate 2,and a p-type body layer 6 is provided on the drain layer 4. A trench 8extends through the body layer 6 as far as the drain layer 4, andincludes a conductive gate 10 insulated from the body layer by a gateinsulator 12. N+ source diffusions 14 are provided adjacent to thetrench.

In use, a voltage is applied to the gate electrode to control a channel16 extending in the body layer 6 adjacent to the trench 8 between thesource 14 and drain 4.

Further details of prior art trench structures are provided in U.S. Pat.No. 6,331,467 to Brown et al, assigned to the US Philips Corporationwhich is incorporated herein by reference.

A problem with this structure is the capacitance between the gate anddrain, since the gate at the bottom of the trench is very close to thedrain. This capacitance can give rise to problems, and in particular tothe Miller effect. The capacitance should therefore be minimised.

A known approach to reducing this capacitance is described in U.S. Pat.No. 6,444,528 to Murphy, which suggests providing a thicker insulator atthe bottom of the trench. U.S. Pat. No. 6,444,528 describes forming asecond trench at the bottom of the trench and growing selective oxide inthe second trench to form this thicker insulator.

However, this approach is complex to manufacture and there isaccordingly a need for a simpler approach to manufacturing suchstructures.

According to the invention there is provided a method of manufacturing atrench gate semiconductor device comprising the steps of: providing asilicon device body having a first major surface, the silicon devicebody having a drain region of a first conductivity type and a bodyregion over the drain region; forming a trench extending downwards intothe silicon device body from the first major surface, the trench havingsidewalls and a base; etching the silicon at the base of the trench toform porous silicon at the base of the trench; and thermally oxidisingthe device to oxidise the porous silicon at the bottom of the trench toform a plug at the base of the trench; and depositing conductivematerial within the trench to form a gate.

By forming porous silicon in the bottom of the trench and then oxidisingit a thick region at the bottom of the trench can be readily formed.This in turn can greatly reduce the gate-drain capacitance and hence theMiller effect. The approach according to the invention is relativelystraightforward to manufacture.

Preferably, the step of etching the bottom of the trench to form poroussilicon includes dry-etching the bottom of the trench through the samemask used to define the trench. The porosity of the silicon can becontrolled by changing the etch chemistry.

Alternatively, the step of etching can include wet-etching.

The side walls of the trench may be provided with a dielectric liner forpreventing the side walls becoming porous. This may be particularlyuseful when a wet etch is used. The liner may be oxide, or alternativelymay be nitride or any other suitable layer. After formation thedielectric liner may be opened at the bottom of the trench, i.e. etchedaway from the bottom of the trench leaving the porous silicon exposed,leaving the dielectric liner on the sidewalls.

A particular benefit of a nitride liner is that it prevents oxidation ofthe sidewalls. This prevents narrowing of the trench during theoxidation step and so reduces the required trench width.

The oxidation step forming the thick oxide at the bottom of the trenchmay also form oxide on the side walls. In one embodiment, this oxide onthe side walls is used as the gate oxide.

In alternative embodiments, the side wall oxide may be etched away. Itis relatively straightforward to etch away the thin oxide formed on theside walls in the thermal oxidation step leaving the bulk of the thickoxide at the bottom of the trench. Where a suitable liner is used, suchas nitride, there may be no oxide formed on the sidewall. In this case,the liner may be etched away.

After removing the liner and/or side wall oxide, gate oxide may beformed by thermal oxidation in a conventional manner.

Following the step or steps of forming the oxide at the bottom of thetrench and the gate oxide the trench may be filled with dopedpolysilicon to form a gate.

In another aspect, there is provided a trench MOSFET comprising: a drainregion of first conductivity type; a body region over the drain region;a trench extending from a first major surface through the body region;source regions of the first conductivity type laterally adjacent to thetrench at the first major surface; thermal gate oxide on the side wallsof the trench; a gate electrode in the trench insulated from the bodyregion by the gate oxide; characterised by a thick oxide plug formed ofoxidised porous silicon at the base of the trench extending into thedrain region.

As explained above, such a structure is relatively straightforward tomanufacture and exhibits a reduced Miller effect.

For a better understanding of the invention, embodiments will now bedescribed, purely by way of example with reference to the accompanyingdrawings in which:

FIGS. 1 a to 1 e show steps in a method of manufacturing a semiconductordevice according to a first embodiment the invention;

FIG. 2 shows an alternative step in a method of manufacturing asemiconductor device according to a second embodiment of the invention;

FIGS. 3 a and 3 b shows an alternative step in a method of manufacturinga semiconductor device according to a third embodiment of the invention;and

FIG. 4 shows a prior art method of manufacturing a semiconductor device.

Like components are given the same reference numerals in the differentfigures. The drawings are not to scale. In this specification whereterms such as “over” and “downwards” are used, these are intended to berelative to the device.

Referring to FIG. 1 a, an n− type epilayer 4 is grown on an n+ typesemiconductor substrate 2. A low doped p− body layer 6 is then formed onthe epilayer 4, for example by ion implantation. Alternatively, the ionimplantation step to form layer 6 may be carried out after the formationof the trench, or the layer 6 may also be grown epitaxially. Thisstructure will be known as the “silicon device body” 1 in thefollowing—the term is not intended to refer to just the body layer 6.The silicon device body has opposed first 22 and second 23 majorsurfaces.

Hard mask 20 is then formed by depositing oxide layer 20 on the firstmajor surface 22 of the silicon device and patterning the oxide layer 20to have an opening 24. Trench 8 is then etched through the opening intothe n− layer 4. This trench etch may be carried out by any knownprocess. The trench has sidewalls 28 and a base 29.

The next step is to form a plug of porous silicon 26 at the bottom ofthe trench 8. The porous silicon is formed from the silicon at thebottom of the trench by etching using a dry etch in a manner known tothose skilled in the art. The porosity of the porous silicon can becontrolled by changing the etch chemistry. FIG. 1 b shows the trenchwith the porous silicon plug 26.

In an alternative etch process, a wet etch may be used. This isparticularly suitable for p-type devices.

As illustrated in FIG. 1 c, conventional thermal oxidation is thencarried out to oxidize the porous silicon 26 to form an oxide plug 30 atthe base of the trench. At the same time, oxide 32 is formed on the sidewall 28 of the trench. Porous silicon can be fully oxidized withoutforming an excessive thickness of oxide 32 on the side walls 28. Thus,the oxide plug 30 at the bottom of the trench is much thicker than theoxide 32 on the side walls.

Optionally, the oxide 32 may be removed by a brief etch process and asecond thermal oxidation step carried out to form gate oxide 12 on theside walls 28 of the trench in place of oxide layer 32. This will benecessary if oxide layer 32 does not have the required thickness to actas a gate oxide, and allows the process parameters for forming the oxideplug 30 to be optimised for oxidising porous silicon and the processparameters for forming the gate oxide layer 12 to be separatelyoptimised for forming gate oxide. Otherwise, oxide 32 forms gate oxide12.

In alternative embodiments with a dielectric liner, especially with anitride dielectric liner, the liner may prevent oxidation of thesidewalls so the oxide 32 will be absent. In this case, the dielectricliner may be etched away and then gate oxide 12 formed on the sidewallsin the conventional manner.

The next step is to fill the trench with polysilicon 34 acting as agate, giving rise to the structure shown in FIG. 1 d.

The remainder of the processing can be carried out in a conventionalmanner, as is well known to the man skilled in the art, to result in adevice schematically illustrated in FIG. 1 e. A source diffusion 14 isimplanted at the first major surface at the lateral edges of the trench.

Source 36, gate 38 and drain 40 contacts are formed. They areschematically illustrated in FIG. 1 e, the drain contact 40 being inthis example a back contact on the second major surface 23. The sourcecontact 36 contacts the n+ source diffusion 14.

The semiconductor is then packaged and contacted to form the finishedsemiconductor device as is known.

This process provides a ready means of manufacturing a trench MOSFETwith a thick oxide plug at the bottom of the trench to reducecapacitance between the gate 10 and the drain 4.

A second embodiment of a method of manufacture is illustrated withreference to FIG. 2. In this alternative, a dielectric liner 50 isformed on the sidewalls 28 and base 29 of the trench after the trench isformed. In the embodiment described, the dielectric liner 50 isdeposited nitride, but alternatively the dielectric liner may be anysuitable dielectric layer, such as oxide or nitride, and may be formed,for example, by oxidation or deposition.

Next, the liner 50 is opened at the base of the trench to expose thesilicon at the base 29 of the trench leaving the liner on the sidewalls,as illustrated in FIG. 2.

Following this, porous silicon is formed at the base of the trench andoxidised as described above with respect to the first embodiment. Thenitride liner 50 prevents oxidation of the sidewalls 28. The dielectricliner 50 is etched away, thermal gate oxide 12 is formed on the walls,and a conductive gate material 34 deposited in the trench to result inan arrangement corresponding to that shown in FIG. 1 d with a smallamount of nitride liner 50 around the oxide plug 30. Processing thencontinues as set out with respect to the first embodiment.

In a still further embodiment, described with reference to FIG. 3, theporous silicon is formed, not by etching the body silicon at the base ofthe trench, but by etching deposited silicon. Thus, after the step offorming the trench as illustrated in FIG. 1, polysilicon 52 is depositedover the hard mask 20 and in the trench 8, as illustrated in FIG. 3 a.Next, the polysilicon is etched back to leave a polysilicon plug 54 atthe base of the trench as illustrated in FIG. 3 b. Processing thencontinues as before by forming porous silicon 26 from the polysiliconplug resulting in the structure shown in FIG. 1 b.

Further details of the processes used may be taken from theaforementioned U.S. Pat. No. 6,331,467. Other process options will beknown to those skilled in the art, and these too may be adopted.

From reading the present disclosure, other variations and modificationswill be apparent to persons skilled in the art. Such variations andmodifications may involve equivalent and other features which arealready known in the design, manufacture and use of trench semiconductordevices and which may be used in addition to or instead of featuresdescribed herein. Although claims have been formulated in thisapplication to particular combinations of features, it should beunderstood that the scope of disclosure also includes any novel featureor any novel combination of features disclosed herein either explicitlyor implicitly or any generalisation thereof, whether or not it mitigatesany or all of the same technical problems as does the present invention.The applicants hereby give notice that new claims may be formulated toany such features and/or combinations of such features during theprosecution of the present application or of any further applicationsderived therefrom.

For example, in the embodiment described the source diffusion 14 isformed after the trench 8. However, as the skilled person will realise,it is also possible to form the source diffusion 14 and then etch thetrench through the source diffusion. Other variations in trench etchmanufacturing may also be used.

The skilled person will realize that the invention may be used in avariety of different semiconductors structures. For example, althoughthe epilayer 4 has been described as an n-epilayer, the body layer 6 asa p-type layer, and the source diffusion 14 as an n-doped region, any orall of these layers may be either p- or n type. A drift region, i.e. alow doped part of the drain epilayer 4 may be used, as is known. Otherlayers, diffusions and contacts may be included if required. The devicemay be p- or n- type.

1. A method of manufacturing a trench gate semiconductor devicecomprising the steps of: providing a silicon device body having a firstmajor surface, the silicon device body having a drain region of a firstconductivity type and a body region over the drain region; forming atrench extending downwards into the silicon device body from the firstmajor surface, the trench having sidewalls and a base; lining thesidewalls of the trench with dielectric liner; etching the silicon atthe base of the trench to form porous silicon at the base of the trench,the dielectric liner formed on the sidewalls of trench preventing thesidewalls from also becoming porous; and thermally oxidizing the deviceto oxidize the porous silicon at the bottom of the trench to form a plugat the base of the trench; and depositing conductive material within thetrench to form a gate.
 2. A method of manufacturing a trench gatesemiconductor device comprising the steps of: providing a silicon devicebody having a first major surface, the silicon device body having adrain region of a first conductivity type and a body region over thedrain region; forming a trench extending downwards into the silicondevice body from the first major surface, the trench having sidewallsand a base: etching the silicon at the base of the trench to form poroussilicon at the base of the trench; and thermally oxidizing the device tooxidize the porous silicon at the bottom of the trench to form a plug atthe base of the trench and to form sidewall oxide on the sidewalls ofthe trench; etching away the oxide formed on the sidewalls and forming agate oxide by thermal oxidation on the sidewalls; and after the step offorming the gate oxide, depositing conductive material within the trenchto form a gate.
 3. A method according to claim 1 wherein the step offorming the trench includes providing a mask on the first major surfacedefining an opening and etching the trench extending downwards from thefirst major surface through the opening.
 4. A method according to claim3 wherein the mask is an oxide hard mask.
 5. A method according to claim3 wherein the step of etching the silicon at the bottom of the trench toform porous silicon includes dry-etching the bottom of the trenchthrough the same mask used to define the trench.
 6. A method ofmanufacturing a trench gate semiconductor device comprising the stepsof: providing a silicon device body having a first major surface, thesilicon device body having a drain region of a first conductivity typeand a body region over the drain region; forming a trench extendingdownwards into the silicon device body from the first major surface, thetrench having sidewalls and a base; depositing a silicon plug in thetrench; etching the silicon at the base of the trench including thesilicon plug to form porous silicon at the base of the trench; thermallyoxidizing the device to oxidize the porous silicon at the bottom of thetrench; and depositing conductive material within the trench to form agate.
 7. A method according to claim 1 further comprising forming asource implant of first conductivity type at the first major surfaceadjacent to the trench and forming source, gate and drain electrodesattached to the source implant, the gate and the drain region at thebottom of the trench respectively to complete the trench gatesemiconductor device.
 8. A method of manufacturing a trench gatesemiconductor device, the method comprising: providing a silicon devicebody having a first major surface, the silicon device body having adrain region of a first conductivity type and a body region over thedrain region; forming a trench extending downwards into the silicondevice body from the first major surface, the trench having sidewallsand a base; lining the sidewalls of the trench with a dielectric liner;etching the silicon at the base of the trench to form porous silicon atthe base of the trench, the dielectric liner formed on the sidewalls oftrench preventing the sidewalls from also becoming porous; thermallyoxidizing the device to oxidize the porous silicon at the base of thetrench to form a plug at the base of the trench, wherein thermallyoxidizing the device forms sidewall oxide on the sidewalls of thetrench; and depositing conductive material within the trench to form agate.
 9. A method of manufacturing a trench gate semiconductor device,the method comprising: providing a silicon device body having a firstmajor surface, the silicon device body having a drain region of a firstconductivity type and a body region over the drain region; forming atrench extending downwards into the silicon device body from the firstmajor surface, the trench having sidewalls and a base; etching thesilicon at the base of the trench to form porous silicon at the base ofthe trench; thermally oxidizing the device to oxidize the porous siliconat the base of the trench to form a plug at the base of the trench,wherein thermally oxidizing the device forms sidewall oxide on thesidewalls of the trench; etching away the sidewall oxide and forming agate oxide by thermal oxidation on the sidewalls of the trench; andafter etching away the sidewall oxide, depositing conductive materialwithin the trench to form a gate.
 10. The method of claim 8, whereinforming the trench includes providing a mask having an opening and onthe first major surface and etching through the opening.
 11. The methodof claim 10, wherein the mask is an oxide hard mask.
 12. The method ofclaim 10, wherein etching the silicon at the base of the trench to formporous silicon includes dry-etching the base of the trench through thesame mask used to define the trench.
 13. The method of claim 10, furthercomprising forming a source implant of the first conductivity type atthe first major surface adjacent to the trench and forming source, gateand drain electrodes attached to the source implant, the gate and thedrain region at the bottom of the trench respectively.